LEON3 PROCESSOR PDF

It also features a built-in disassembler for debug purposes. It is thus possible to instantiate several processor cores in the same design with different configurations. The LEON3 template designs can be configured using a graphical tool built on tkconfig from the linux kernel. This allows new users to quickly define a suitable custom configuration. The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces.

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In my case was the number Like this Makefile. Now, if you want generate the linux image, you just need to do a "make" on snapgear-p33 path When you boot the linux from FPGA you will see these lines: Loading theora In my case I used the ioremap.

Youshould do this once and keep the pointer returned from ioremap and usethis to access the hardware in the rest of the code. Soft lockup is when the kernel fails to reschedule for 10 seconds.

Thisimplies that your driver does not yield the CPU. You may not busy wait. You can receive back the data in order to compare the output. Beyond this, we need to send the height and the width, because the videocontroller will request. My new leon3mp is leon3mp. There was some bugs on video controller and that size of buffer was not necessary, but if changed the size to a video of 96x80 , it was not running.

These bugs are solved, but I just decode a video of 96x80 resolution. It will be futurely solved when the external memory is implemented. Cross-clock domain I had some difficult in to plug it on Leon, because of hardware constrains. The clock frequency used by video controller is of 25 MHz, but the frequency of Leon system is of 50 MHz. It was not just to put a simples clock divider, because on the synthesis a had problems of cross-clock domain at time analysis.

It was generating a clock skew problems. The solution was simples, I needed to change some parameters on PLL of Leon system, the PLL phase-locked loop is basically a closed loop frequency control system that generate the clocks of Leon and sdram with the phase adjusted, I needed to include a new clock there with the correct parameters.

If run a video of 96x72, I will have a video of 96x Something like: Ogg logical stream c6ca0 is Theora 96x80 Littles purple points on video At first tests, there were littles purple points on the image, It needed of a shift phase on video controller clock 25 MHz.

We think that the reading of video controller memory was happening at the same phase of writting. Demostration I did a demonstration of this integration until the video controller and it is on youtube.

The Unknown device is the Theora Hardware, it is not show the name "Theora Hardware" because I am using a evaluation version of Grmon; - Open the kermit interface and set the configuration by Serial Interface ; - Run the linux kernel using grmon, by USB Blaster - jtag ; - Come back to kermit and you will see a konsole of Linux by Serial Interface.

There are basically one problem in this presentation. On NIOS, a video was running very slow, almost 7 times. A video of 15 second is taking 75 seconds 5 times. Without the LINUX, a video 30 seconds encoded with the best quality ffmpeg2theora -x 96 -y 80 -v 10 -e 30 original.

Below I will discribe this other implementation. Putting a ogg video a seeing a video on monitor. We are working with a 96x80 of resolution, that video on youtube was duplicating the output pixels.

The next step will be to do plug it the system [b] on the SRAM memory in order to increase the resolution.

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HiRel Microelectronics

In my case was the number Like this Makefile. Now, if you want generate the linux image, you just need to do a "make" on snapgear-p33 path When you boot the linux from FPGA you will see these lines: Loading theora In my case I used the ioremap. Youshould do this once and keep the pointer returned from ioremap and usethis to access the hardware in the rest of the code.

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Hardware implementation of Theora decoding

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